Can you elaborate a little one what particular additional details you require? Programming is permitted in the application. The user program should not be use this space if IAP flash Which results in a flash write/erase operation, use 32 bytes of space in the top portion of The flash memory is not accessible during a write or erase operation. The IAP flash programming commands use the top 4 bytes of on-chip RAM. The ISP flash programming commands use the top 4 bytes of on-chip RAM. Stack usage is 640 bytes (0x280) and grows downwards. The stack of UART ISP commands is located at address 0x1000 03A8. The interrupt vectors residing in the boot block of the on-chip flash memory also become active after reset, that is, the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000. The RAM usage is described in Section 4.3.7 “ISP interrupt and SRAM use”.
The bootloader is designed to run from this memory area, but both the ISP and IAP software use parts of the on-chip RAM. The boot block is located in the memory region starting from address 0x0F00 0000. I am have not been able to confirm this, however it leaves me reluctant to relocate the memory usage of our application without a well-defined memory usage specification.Įxcerpt from UM11065 rev 1.3 (pages 15, 21 and 34): Our earlier testing may have used a different ROM version using less stack space. This ends up overwriting the top 44 bytes (0x1000 0FD4 - 0x1000 0FFB) during a normal startup. Debugging shows that version 13.1 of the boot ROM places its initial stack at the end of RAM and adopting a lower stack only on entering ISP mode. We have recently encountered a problem with memory outside of these ranges being overwritten on reset.
The user manual defines the memory usage of the bootloader in the sections quoted below and I had interpreted the text as the boot ROM using 0x1000 0128 - 0x1000 03A7 and 0x1000 0FE0 - 0x1000 0FFF only. Which areas of RAM are guaranteed to not to be overwritten by any previous of future versions of the LPC804 boot ROM? I am only interested in normal reset and IAP programming, ISP mode is not required. This requires selecting an area which the boot ROM will not overwrite during the reset. Our application needs to preserve a block of RAM memory across software reset.